1. Field of the Invention
The present invention relates to an adjusting circuit, and particularly relates to an adjusting circuit for a delay circuit.
2. Description of the Prior Art
Delay circuits are usually utilized for synchronizing a plurality of clocks. Normally, delay circuits can be classified into analog delay circuits and digital delay circuits.
FIG. 1 is a schematic diagram illustrating a prior art analog delay circuit 100, which utilizes an input clock to generate a plurality of delay clocks with the same frequency but different phases. As shown in FIG. 1, the delay circuit 100 comprises: a phase detector 102, a charge pump 104, a loop filter 106, and a delay line 108. The input clock CKIN (with a period T) is an input signal of the delay circuit 100. The control voltage Vctrl from the loop filter 106 adjusts the delay effect of the input clock CKIN by using the delay stages of the delay line 108. In this case for example, the delay line 108 includes N delay stages in series (not illustrated), and the delay clock from the m-th delay stage is CKm. The delay clock CKN of the last delay stage falls behind the input clock CKIN by a delay period of Td. The phase detector compares the phase difference between the input clock CKIN and the delay clock CKN to generate a rising control signal UP and a falling control signal DOWN, in order to control the charge pump 104, which outputs the control voltage Vctrl via the loop filter 106, thereby increasing or decreasing Td.
A variety of digital delay circuits are well known to those of ordinary skills in the art; therefore, details are thus omitted here for brevity. A conventional digital delay circuit includes a delay line having a plurality of delay stages (for example, an inverter) and utilizes a multiplexer (MUX), an inverter or other types of digital devices to control the delay stage.
Both analog and digital delay circuits have their disadvantages. The delay circuit 100 shown in FIG. 1 includes several components, and therefore occupies massive circuit area. An analog circuit provides low accuracy and needs extra circuits for control. However, delay stages of a digital delay circuit are easily affected by process, voltage, and temperature (PVT), causing errors between the signals obtained and expected. Furthermore, a digital delay circuit will require a longer delay line if reaching different operation frequencies is desired. For example, if the operation frequency is required to be X-times higher, then a delay line that is longer by a multiple of X-times is required.
Thus, a new invention is needed to solve the above-mentioned problems.